As modern integrated circuits shrink in size, the associated features shrink in size as well. As transistor shrink, features such as through vias and other electroplated elements shrink in size as well. In many instances, various layers of circuit on chips, dies, in packages, on PCBs and other substrates are interconnected between various layers by way of vias. Typically, the vias are connected to traces or other conductive structures to route electrical signals through dielectric layers. One way of forming a conductive interconnect in a via or trench opening is to form the opening and then plate a conductive metal in the inside of the opening. In some instances, copper, gold, aluminum or other material are plated in the via/trench openings.
The plating process may be performed by electroplating, where an electric current is used to transfer metal in an aqueous solution to a surface. In order to facilitate the plating process, a seed layer may be deposited prior to electroplating. The seed layer provides nucleation sites where the electroplated metal initially forms. The electroplated metal deposits more uniformly on a conformal and even seed layer than on a bare dielectric.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.